Abstract; In this paper, a design for testability of 10 bits continuous time sigma delta ADC is presented. This new full test technique provides: simple way, 2 external lines and high testability for the circuit’s performances. This test is used for different sub-circuits evaluation and characterization to determine the contribution of each part in the […]
October 16, 2019 Rachid SIKADOUR 2013, Microelectronic & Nanotechnologie Division, Team CDS Design for testability (DfT)Continuous time sigma delta ADCDesign of CMOS integrated circuit
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