Abstract; Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs). In an SoC, the placement of the communicating elements across the network has an impact on system performance. Such a placing is called the MAPPING phase in networks on chip design process. Many approaches dealing with the mapping phase have been […]
October 15, 2019 Rachid SIKADOUR 2017, Microelectronic & Nanotechnologie Division, Tools, Digital Circuits and Systems Design Team Network on chip, placing, topology
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