Analog Design for Testability Technique for First Order Sigma Delta ADC


In this paper, a design for testability of 10 bits continuous time sigma delta ADC is presented. This new full test technique provides: simple way, 2 external lines and high testability for the circuit’s performances. This test is used for different sub-circuits evaluation and characterization to determine the contribution of each part in the total ADC error thus the ADC design can be improved. Using standard CMOS 0.24 μm technology this technique is implemented, the obtained results confirm that the presented technique ensures a high ADC testability, and the suitability for use with integrated circuit (IC) post development design is demonstrated.