This paper presents a new attempt to more understand negative bias temperature instability (NBTI) stress in semiconductor devices. NBTI impact has been experimentally investigated on both p-substrate MOS (nMOS-capacitor) and nMOS transistors under accumulation condition, and new findings have been revealed. Indeed, nMOS-capacitor’s flat band shift (VFB) under NBTI stress has disclosed that time exponent (n) and activation energy (Ea) do vary with applied voltage stress pointing out to the contribution of two components, interface (NIT) and oxide (NOT) traps. Besides, the threshold electric field delimiting NBTI and stress induced leakage current (SILC) can be well established. These findings have been confirmed by the appearance of a turn-around effect in nMOS transistors under NBTI stress. Moreover, charge pumping characterization has unveiled that NBTI degradation in nMOS transistor goes through two stages. First, only NIT is created, then simultaneous generation of NIT and oxide traps (NOT) takes part.